With a rapid increase of the integration density of semiconductor memory chips in recent years, more than ten millions of cells are typically integrated in a single memory chip. Increasing number of integrated cells in the chips is inevitably accompanied by an extension of a time for testing defects of cells. For that reason, a general test inferiority test circuit often employs a data compression test mode to shorten a time for testing defects of cells.
Such a data compression test mode means a scheme inputting/outputting data through a part of input/output pins DQ used in a normal mode and coincidentally testing inferiority from a plurality of cells accessed by the same address.
A conventional cell inferiority test circuit using the data compression test mode is configured as follows by referring to FIG. 1.
As shown in FIG. 1, the conventional cell inferiority test circuit generates compression data, which contains information about inferiority of cells, by compressing right data RDATA<1:16> or left data LDATA<1:16> selected in response to the first and second selection signals TPARA<1:2>. The compression data is loaded on a global input/output line GIO in sync with a strobe signal IOSTR.
However, the general cell inferiority test circuit is short of loading performance on the global input/output line GIO because of an insufficient timing margin between the strobe signal IOSTR and the compression data due to PVT variations.